In the field of integrated circuit devices, for many modern embedded applications there is a need for serialisation of timer channels etc. in order to reduce the number of pins required implement such timer channels between, say, a microcontroller unit (MCU) of the embedded application and external devices operably coupled thereto. For clarity, such a timer channel may comprise, by way of example, a timing control signal to an external hardware component that generates input/output required to, say, switch at times dependent on user configurations or the like. For example, such a timer channel may comprise a single timing control signal to an external hardware component arranged to generate a pulse-width modulated (PWM) output. Accordingly, the scheduling of such timer channels is of importance in order to ensure correct operation of the components reliant thereon.
Serial peripheral interface (SPI) frames are often used to send control data to the same external devices for which the timer channels are required. As such, it is conventional for SPI frames and timer channels to be transmitted over the same communications channel, whereby SPI frames are interleaved with the serialised timer channels.
A challenge faced by manufacturers of embedded semiconductor devices for use within such systems is that different applications require unique rules for determining when SPI frames may be interleaved within the serialised timer channels, for example in order to avoid jitter of the serialised timer channels. There is currently no common standard approach to determining how such interleaving of SPI frames within timer channels should be implemented. As such, manufacturers of embedded semiconductor devices for use within such systems are faced with different requirements from different customers in terms of controlling the interleaving of SPI frames within the timer channels. It is desirable, from a manufacturer's point of view, to be able to develop and manufacture a single integrated circuit (IC) device that is capable of supporting the interleaving requirements of multiple customers for different applications.
For applications such as automotive applications, in which high speed scheduling of the SPI frames and timer channels being transmitted over a shared communications channel is required, it is known to use hard state machines to perform the required (high speed) scheduling and interleaving. However, a problem with using hard state machines in this manner is that they are typically limited to implementing a particular interleaving rule set. Accordingly, in order to enable support within a single IC device using such hard state machines, it is necessary to provide multiple hard state machines within the IC device. The inclusion of multiple hard state machines undesirable increases the die size of the IC device, and increases development time due to the need for designing, testing and validating the multiple hard state machines.
A software based implementation in which the scheduling of the SPI frames and timer channel is performed by software would enable a flexible implementation to be provided. However, such an implementation would have a significant impact on the processing performance of the MCU, for example requiring up to 50% of the processing capabilities of a 200 MHz processor to achieve a 1 μs transmit period.